An essential step in the manufacture of all integrated circuit devices is known as “packaging” and involves mechanical and environmental protection of a silicon chip which is at the heart of the integrated circuit as well as electrical interconnection between predetermined locations on the silicon chip and external electrical terminals.
At present three principal technologies are employed for packaging semiconductors: wire bonding, tape automatic bonding (TAB) and flip chip.
Wire bonding employs heat and ultrasonic energy to weld gold bonding wires between bond pads on the chip and contacts on the package.
Tape automatic bonding (TAB) employs a copper foil tape instead of bonding wire. The copper foil tape is configured for each specific die and package combination and includes a pattern of copper traces suited thereto. The individual leads may be connected individually or as a group to the various bond pads on the chip.
Flip chips are integrated circuit dies which have solder bumps formed on top of the bonding pads, thus allowing the die to be “flipped” circuit side down and directly soldered to a substrate. Wire bonds are not required and considerable savings in package spacing may be realized.
The above-described technologies each have certain limitations. Both wire bonding and TAB bonding are prone to bad bond formation and subject the die to relatively high temperatures and mechanical pressures. Both wire bond and TAB technologies are problematic from a package size viewpoint, producing integrated circuit devices having a die-to-package area ratio ranging from about 10% to 60%.
The flip-chip does not provide packaging but rather only interconnection. The interconnection encounters problems of uniformity in the solder bumps as well as in thermal expansion mismatching, which limits available substrates to silicon or to materials which have thermal expansion characteristics similar to those of silicon.
Conventional semiconductor packaging terminology has defined the term chip scale packaging to include any packaging process with a ratio of packaging to die less than or equal to 1.2:1. Additionally, the packaging layer conventionally provides protection to the encased semiconductor or integrated circuit.